Digital Electronics and Logic Design MCQs 2026

Asynchronous (ripple) counter has

1. Aall FFs clocked by common edge simultaneously✓
2. Bflip-flops clocked by previous stage output✓
3. Cno flip-flops only combinational logic✓
4. Donly shift register without counting✓

Clock skew between flip-flops can cause

1. Aguaranteed faster operation always✓
2. Belimination of metastability without limit✓
3. Cinfinite fan-out capability✓
4. Dtiming violations if effective setup/hold margins are reduced✓

Scan flip-flop design aids

1. Aonly analog amplification✓
2. Bonly power factor correction✓
3. Ctesting by serially shifting test vectors through the chain✓
4. Donly rectifier ripple reduction✓

Level-sensitive latch differs from edge-triggered FF in that it

1. Ais transparent while enable is active✓
2. Bchanges only on clock edge always✓
3. Ccannot store any state✓
4. Drequires JK inputs only✓

Register is constructed from

1. Aonly combinational gates without memory✓
2. Bmultiple flip-flops storing parallel bits on common clock✓
3. Csingle diode rectifier✓
4. Dop-amp integrator only✓

Flip-flop propagation delay tpd is

1. Asetup plus hold only without output delay✓
2. Btime from clock edge to valid output change at Q✓
3. Cclock period definition only✓
4. Drise time of power supply only✓

Metastability occurs when

1. Ainputs are stable with large setup margin✓
2. Bpower supply is perfectly regulated✓
3. Conly in combinational logic without storage✓
4. Dsetup or hold time is violated and output dwells between valid logic levels✓

Master-slave flip-flop reduces

1. Aneed for setup time entirely✓
2. Bclock frequency to DC only✓
3. Crace conditions by separating capture and output update✓
4. Dpower supply decoupling✓

Asynchronous preset and clear on flip-flops

1. Aoverride clocked operation immediately when asserted✓
2. Bonly work on clock edge like D input✓
3. Cdisable all outputs to high-Z always✓
4. Dreplace the need for power supply✓

Hold time of flip-flop is

1. Atime before clock edge only✓
2. Bpropagation delay from clock to Q only✓
3. Cminimum time data must remain stable after active clock edge✓
4. Dfrequency of oscillator only✓

Setup time of flip-flop is

1. Aminimum time data must be stable before active clock edge✓
2. Btime after clock edge for output change✓
3. Chold time after edge only without setup✓
4. Dclock period only✓

T flip-flop toggles output when

1. AT is 0 at clock edge✓
2. Breset is deasserted only✓
3. CT input is 1 at active clock edge✓
4. Dpreset alone without clock✓

JK flip-flop toggles when

1. AJ=0 and K=0 always✓
2. BJ and K are both 1 at active clock edge✓
3. Conly asynchronous reset is asserted✓
4. Dclock is held LOW indefinitely✓

Positive-edge-triggered flip-flop changes state on

1. Afalling edge only always✓
2. Brising edge of clock✓
3. Cany DC level without transition✓
4. Dboth edges simultaneously✓

D flip-flop eliminates

1. Aneed for clock entirely✓
2. Ball propagation delay✓
3. Cindeterminate condition of SR latch by using single data input✓
4. Dreset pin unconditionally✓

SR latch built with NOR gates has invalid state when

1. Aboth inputs are 0✓
2. Bonly S is 0✓
3. Conly R is 0 with S pulsed✓
4. DS and R are both 1 simultaneously (active-high inputs)✓

K-map method is limited compared to Quine-McCluskey for

1. Abeing less accurate always✓
2. Binability to handle don′t-cares ever✓
3. Crequiring software always✓
4. Dmanual convenience on few variables rather than algorithmic scalability✓

Overlapping groups in K-map are allowed because

1. Aeach minterm can appear in only one group always✓
2. Boverlap invalidates simplification✓
3. Ca minterm may participate in multiple groups to form larger coverings✓
4. Donly diagonal overlap is permitted✓

Five-variable K-map is often implemented as

1. Asingle row of five cells only✓
2. Bcircular map without Gray code✓
3. Ctruth table without grouping✓
4. Dtwo four-variable maps with shifting variable✓

SOP form obtained from K-map is a sum of

1. Aonly single literals without products✓
2. BPOS maxterms only✓
3. CNAND operations without OR✓
4. Dproduct terms (AND terms ORed together)✓

Redundant group in K-map is one that

1. Ais the smallest possible group always✓
2. Bcovers only don′t-cares without 1s✓
3. Cdoes not cover any minterm not already covered by essential groups✓
4. Dcannot be formed on the map✓

Number of cells in K-map for n variables is

1. An × 2 only✓
2. B2^n✓
3. Cn^2 without exponent✓
4. D2n only✓

For POS minimization using K-map, groupings are made on

1. Azeros (or maxterms) to obtain sum terms✓
2. Bonly 1s without zeros ever✓
3. Cdon′t-cares only without zeros✓
4. Doutput column of truth table only✓

Digital clock application uses counters for

1. Aonly DAC conversion without timing✓
2. Bonly rectifier filtering✓
3. Cfrequency division and time display multiplexing✓
4. Donly motor slip measurement✓

Cascade counters achieve

1. Aonly single-digit BCD without linkage✓
2. Belimination of clock signal✓
3. Chigher modulus by connecting carry/borrow between stages✓
4. Dpurely analog integration without FFs✓

Synchronous counter typically has

1. Ahigher cumulative delay than ripple always✓
2. Bno clock input requirement✓
3. Conly one flip-flop regardless of modulus✓
4. Dlower propagation delay uncertainty than ripple counter of same width✓

Terminal count output of counter indicates

1. Aalways midpoint count only✓
2. Bmaximum count reached in the sequence✓
3. Crandom logic level without definition✓
4. Danalog ramp completion only✓

Frequency division by 2 per stage in binary counter means

1. Aeach successive FF toggles at half the previous stage frequency✓
2. Ball stages share identical frequency✓
3. Cfrequency doubles each stage✓
4. Dno relation to clock frequency✓

Presettable counter can be loaded with

1. Aonly zero without load capability✓
2. Banalog voltage on op-amp input only✓
3. Conly serial shift without parallel load✓
4. Dparallel data to start from a specific initial value✓

Glitch problem in asynchronous ripple counter occurs because

1. Astages change at slightly different times producing brief false counts✓
2. Ball bits change simultaneously always✓
3. Cclock is perfectly synchronous by definition✓
4. Doutputs are analog without discrete levels✓

Counter modulus reduction uses

1. Aonly increasing clock frequency without feedback✓
2. Bfeedback logic to skip states and achieve desired modulo✓
3. Cremoving all flip-flops✓
4. Danalog RC timing without digital logic✓

Johnson counter (twisted ring) has sequence length of

1. An states only✓
2. B2^n states always like binary✓
3. C2n for n flip-flops✓
4. Done state only✓

Ring counter is implemented with

1. Aone hot circulating bit among flip-flops✓
2. Bbinary weighted sum only without circulation✓
3. CJohnson sequence inverted feedback only✓
4. DK-map groups only✓

Up-down counter can

1. Aonly count up without down mode✓
2. Bincrement or decrement count on clock depending on control✓
3. Conly operate asynchronously without clock✓
4. Dstore analog samples without digital states✓

Decade counter (BCD) counts

1. A0 through 15 in binary always✓
2. Bonly even numbers✓
3. Canalog voltage levels without digits✓
4. D0 through 9 then returns to 0✓

Modulo-N counter repeats count sequence every

1. A2^N states always without exception✓
2. BN squared states✓
3. CN states✓
4. Done clock period only✓

Synchronous counter has all flip-flops clocked by

1. Aprevious stage Q output only✓
2. Bcommon clock signal✓
3. Casynchronous preset only without clock✓
4. Drandom noise transitions✓

Wrap-around adjacency on K-map means

1. Aonly interior cells can group✓
2. Bedge cells are considered adjacent across map boundaries✓
3. Cdiagonal cells always adjacent✓
4. Dcells two steps apart are adjacent✓

Essential prime implicant is

1. Aa prime implicant that covers at least one minterm not covered by any other prime implicant✓
2. Bany group of two cells only✓
3. Calways the largest group without uniqueness✓
4. Doutput of OR gate without minimization✓

Don′t-care conditions in K-map are marked as

1. Aalways 0 without choice✓
2. Balways 1 without choice✓
3. CX and may be assigned 0 or 1 to maximize groups✓
4. Dignored without affecting simplification ever✓

A group of 8 adjacent 1s on a 4-variable K-map eliminates

1. Athree variables✓
2. Bone variable only✓
3. Call four variables always without remainder✓
4. Dno variables✓

A group of 4 adjacent 1s in a K-map eliminates

1. Aone variable only✓
2. Bthree variables always✓
3. Ctwo variables from the product term✓
4. Dno simplification✓

A group of 2 adjacent 1s in K-map eliminates

1. Atwo variables always✓
2. Bno variables ever✓
3. Cone variable from the product term✓
4. Dall variables in the expression✓

Adjacent cells in a K-map differ by

1. Atwo variables always✓
2. Bone variable only (Gray code adjacency)✓
3. Call variables simultaneously✓
4. Dno systematic rule✓

Karnaugh map is used for

1. Ameasuring propagation delay in oscilloscope✓
2. Bcalculating Fourier coefficients only✓
3. Cdetermining ADC resolution only✓
4. Dsimplifying Boolean expressions graphically✓

Buffer gate is used to

1. Ainvert all inputs always✓
2. Bstore one bit of memory✓
3. Cisolate loads and restore signal levels without inversion✓
4. Ddivide clock frequency by two without flip-flop✓

TTL logic HIGH level is typically

1. A0 V always for HIGH✓
2. B12 V without regulation✓
3. Cfloating undefined as HIGH without pull-up✓
4. Daround 2.4 V minimum at output for 5 V family✓

CMOS logic dissipates significant power primarily during

1. Asteady state with inputs fixed at valid levels✓
2. Bonly when output is high-Z✓
3. Conly at DC with no capacitive load✓
4. Dswitching transitions when both PMOS and NMOS briefly conduct✓

Noise margin indicates

1. Amaximum clock frequency only✓
2. Bchip area in mm² only✓
3. Conly DC supply current✓
4. Dallowable noise on input before logic level is misinterpreted✓

Propagation delay of a logic gate is

1. Atime between input transition and corresponding output transition✓
2. BDC noise margin only✓
3. Cpower dissipation in watts only✓
4. Dnumber of pins on package✓

Tri-state buffer third state is

1. Aalways logic 1✓
2. Bhigh-impedance output disconnected from logic levels✓
3. Calways logic 0✓
4. Dshort circuit to ground✓

Fan-out of a logic gate specifies

1. Amaximum number of similar gate inputs it can drive reliably✓
2. Bpropagation delay only✓
3. Csupply voltage tolerance only✓
4. Dnumber of product terms in SOP✓

Positive logic defines HIGH as

1. Alogic 1 and LOW as logic 0✓
2. Blogic 0 as HIGH always✓
3. Canalog voltage without digital levels✓
4. Dfloating input as definite 1✓

De Morgan theorem states (A · B)′ equals

1. AA′ + B′✓
2. BA′ · B′✓
3. CA + B✓
4. DA ⊕ B✓

XNOR gate is also called

1. Ainverter only✓
2. Bequivalence gate✓
3. Cbuffer only✓
4. Ddemultiplexer✓

XOR gate output is 1 when

1. Ainputs are different✓
2. Binputs are equal✓
3. Call inputs are 0 only✓
4. Dboth inputs are 1 only✓

NOR gate as a universal gate can implement

1. Aonly AND functions without NOT✓
2. Bonly buffers without inversion✓
3. Conly XOR without other gates✓
4. Dany Boolean function given enough gates✓

OR gate output is HIGH when

1. Aall inputs are LOW only✓
2. Bany input is HIGH✓
3. Cinputs are equal always✓
4. Donly when inputs differ✓

NAND gate is functionally equivalent to

1. Ainverted OR only without AND✓
2. Bdirect AND without inversion✓
3. Cexclusive OR of inputs✓
4. Dinverted AND of its inputs✓

The Boolean expression for output of AND gate is

1. AY = A · B✓
2. BY = A + B✓
3. CY = A ⊕ B✓
4. DY = A′✓