Analog Electronics MCQs 2026

58 questions with detailed answers · 19 from past papers · 6 quiz batches available

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Page 1 of 1Questions 1–10 of 58
  1. Q1Past Paper · PPSC/FPSC/NTSmedium

    Transformer coupling in amplifiers provides

    1. Ainfinite bandwidth without leakage inductance
    2. Belimination of all AC coupling
    3. CDC isolation and impedance matching between stages
    4. Ddirect connection of base to collector
    💡 Explanation:

    Transformer passes AC while blocking DC; can match impedances.

  2. Q2hard

    Total harmonic distortion (THD) measures

    1. Aonly DC offset magnitude
    2. Bonly noise floor without harmonics
    3. Charmonic content relative to fundamental in output
    4. Dslew rate limit only
    💡 Explanation:

    THD quantifies nonlinear distortion products.

  3. Q3medium

    Differential amplifier rejects

    1. Adifferential signals between inputs
    2. Bcommon-mode signals applied equally to both inputs
    3. Csignals on inverting input only without any gain
    4. Dsupply voltage variations as common-mode always without CMRR limit
    💡 Explanation:

    Matched pair cancels equal inputs; amplifies difference.

  4. Q4Past Paper · PPSC/FPSC/NTShard

    Cascode amplifier configuration improves

    1. Ahigh-frequency response by reducing Miller effect
    2. Bonly DC offset without frequency benefit
    3. Cinput impedance to near zero always
    4. Doutput to be digital logic level only
    💡 Explanation:

    Stacked devices isolate voltage swing at input device drain.

  5. Q5medium

    Negative feedback in amplifiers generally

    1. Aincreases distortion without exception
    2. Beliminates need for power supply
    3. Creduces distortion and stabilizes gain at the cost of bandwidth
    4. Draises open-loop gain
    💡 Explanation:

    Feedback trades gain for linearity and predictability.

  6. Q6medium

    Bandwidth of an amplifier is often defined between

    1. Alower and upper half-power (−3 dB) frequencies
    2. Bonly DC gain point
    3. Conly harmonic distortion threshold without frequency
    4. Dsupply ripple frequency only
    💡 Explanation:

    −3 dB points mark significant gain rolloff limits.

  7. Q7Past Paper · PPSC/FPSC/NTSmedium

    Bypass capacitor across emitter resistor in CE stage

    1. Aincreases AC gain by shorting emitter resistance at signal frequency
    2. Breduces AC gain to zero always
    3. Cblocks AC to the base
    4. Dreplaces collector load
    💡 Explanation:

    AC ground at emitter removes degeneration for signal.

  8. Q8easy

    Coupling capacitor between amplifier stages blocks

    1. AAC signal entirely without DC block
    2. Bonly high frequencies above 1 MHz always
    3. Cfeedback path unconditionally
    4. DDC bias while passing AC signal
    💡 Explanation:

    Capacitor passes AC but prevents DC level shift propagation.

  9. Q9medium

    Class AB amplifier improves on Class B by

    1. Aeliminating all feedback
    2. Bproviding small bias so both devices conduct near crossover
    3. Cusing only single transistor
    4. Doperating only in cutoff always
    💡 Explanation:

    Slight overlap reduces crossover distortion.

  10. Q10Past Paper · PPSC/FPSC/NTSmedium

    Class B push-pull amplifier each transistor conducts for

    1. Afull 360° each simultaneously
    2. Bapproximately 180° of the cycle
    3. C90° only without crossover region
    4. D0° so no output ever
    💡 Explanation:

    Each device handles one half-cycle; crossover distortion possible.

  11. Q11easy

    Class A amplifier conducts

    1. Aonly 180° of cycle
    2. Bless than 90° only
    3. Conly during negative half-cycle
    4. Dfor the full 360° of the input cycle
    💡 Explanation:

    Quiescent current flows continuously; conduction angle 360°.

  12. Q12easy

    Power amplifier is designed to deliver

    1. Aonly microvolt signals to high-impedance probes
    2. Blogic levels to CMOS gates only
    3. Csignificant power to the load efficiently
    4. DDC offset calibration only
    💡 Explanation:

    Output stage handles large voltage-current product to load.

  13. Q13Past Paper · PPSC/FPSC/NTSeasy

    Voltage amplifier ideally increases

    1. Acurrent without voltage change
    2. Bpower factor of mains only
    3. Csignal voltage with minimal loading of source
    4. Dfrequency of carrier without gain
    💡 Explanation:

    Voltage gain Av = Vout/Vin in small-signal models.

  14. Q14hard

    Rail-to-rail op-amp output stage allows

    1. Aoutput fixed at mid-supply only
    2. Binput only on positive rail without negative
    3. Coperation without power supplies
    4. Doutput swing close to both supply rails
    💡 Explanation:

    Extended output range maximizes dynamic range on low supplies.

  15. Q15medium

    Schmitt trigger using op-amp provides

    1. Apure integration without thresholds
    2. Bzero output swing always
    3. Cinfinite CMRR without resistors
    4. Dhysteresis to avoid chatter on noisy input signals
    💡 Explanation:

    Positive feedback creates upper and lower threshold levels.

  16. Q16Past Paper · PPSC/FPSC/NTShard

    Gain-bandwidth product of an op-amp is approximately constant for

    1. Aall frequencies without rolloff
    2. Bsingle-pole dominant response in closed-loop designs
    3. CDC offset only
    4. Dcomparator hysteresis only
    💡 Explanation:

    GBW ≈ AOL × BW; closed-loop bandwidth trades with gain.

  17. Q17medium

    Input bias current of op-amp is

    1. AAC ripple on output only
    2. Bslew rate in V/μs
    3. Cclosed-loop gain in dB only
    4. Daverage DC current required by the input terminals
    💡 Explanation:

    Bias current flows into BJT bases or FET leakage paths.

  18. Q18Past Paper · PPSC/FPSC/NTSeasy

    Op-amp comparator output saturates to

    1. Aalways mid-rail without saturation
    2. Banalog value proportional to difference in linear mode always
    3. Cnear positive or negative supply depending on input difference
    4. Dzero without supply
    💡 Explanation:

    Without negative feedback op-amp acts as high-gain comparator.

  19. Q19medium

    Differentiator op-amp circuit uses

    1. Aonly resistors in both paths
    2. Binductor in feedback without capacitor
    3. Ccapacitor at the input and resistor in feedback
    4. DZener diode for clipping only
    💡 Explanation:

    Capacitor passes high-frequency components for differentiation.

  20. Q20medium

    Integrator op-amp circuit uses

    1. Ainductor in input only without capacitor
    2. Bcapacitor in the feedback path
    3. Cresistor-only feedback for integration
    4. Ddiode bridge in feedback
    💡 Explanation:

    Capacitor integrates input current producing output ∝ ∫vin dt.

  21. Q21Past Paper · PPSC/FPSC/NTSeasy

    Unity-gain buffer (voltage follower) uses

    1. Apositive feedback only
    2. B100% negative feedback from output to inverting input
    3. Cno feedback connection
    4. Dopen-loop operation only
    💡 Explanation:

    Non-inverting input driven; output fed back for V+ ≈ V−.

  22. Q22medium

    Common-mode rejection ratio (CMRR) measures

    1. Adifferential gain only without common signal
    2. Boutput short-circuit current only
    3. Csupply voltage ripple only
    4. Dability to reject equal signals applied to both inputs
    💡 Explanation:

    High CMRR suppresses noise appearing on both inputs.

  23. Q23medium

    Freewheeling diode across an inductive load prevents

    1. Alarge voltage spikes when switching current off
    2. Bforward voltage drop from existing
    3. Coscillator startup without feedback
    4. Dop-amp input offset drift
    💡 Explanation:

    Diode provides path for inductive current decay.

  24. Q24medium

    Slew rate of an op-amp limits

    1. Amaximum rate of change of output voltage
    2. BDC gain only
    3. Cinput bias current only
    4. Dcommon-mode rejection at DC only
    💡 Explanation:

    Internal current limits cap dVout/dt especially for large steps.

  25. Q25medium

    Transconductance gm of a FET relates

    1. Asmall-signal drain current change to gate-source voltage change
    2. Bcollector current to base current only
    3. Cdiode forward voltage to current only
    4. Doutput voltage to supply voltage only
    💡 Explanation:

    gm = ∂ID/∂VGS at the Q-point.

  26. Q26hard

    Depletion-mode MOSFET differs from enhancement mode in that it

    1. Anever conducts without positive VGS always
    2. Bhas no channel at manufacture
    3. Cuses only PNP structure
    4. Dconducts with VGS = 0 and requires negative VGS to turn off (n-channel)
    💡 Explanation:

    Depletion devices have built-in channel doping.

  27. Q27Past Paper · PPSC/FPSC/NTSeasy

    Enhancement-mode n-channel MOSFET conducts when

    1. AVGS exceeds threshold voltage positively
    2. BVGS is zero without channel ever
    3. CVDS alone creates channel without gate
    4. Dgate is left floating for heavy conduction
    💡 Explanation:

    Positive VGS above Vth induces inversion layer.

  28. Q28easy

    MOSFET is a

    1. Avoltage-controlled device via gate-source voltage
    2. Bcurrent-controlled device like BJT base
    3. Cmajority carrier device only in depletion mode always without exception
    4. Dbipolar device with two PN junctions
    💡 Explanation:

    Gate field controls channel conductivity.

  29. Q29hard

    Early effect in a BJT causes

    1. Agate threshold to decrease only in MOSFET
    2. Bcollector current to increase slightly with collector-emitter voltage
    3. Cdiode PIV to double
    4. Dinductor core saturation
    💡 Explanation:

    Base-width modulation raises IC with increasing VCE.

  30. Q30Past Paper · PPSC/FPSC/NTSmedium

    Common-collector (emitter follower) configuration has

    1. Alow input and high output impedance
    2. Bhigh input impedance and low output impedance
    3. Cvoltage gain much greater than 100 typically
    4. Dinverted output relative to input always
    💡 Explanation:

    Emitter follower provides unity voltage gain with buffering.

  31. Q31medium

    BJT operates in saturation when

    1. Acollector-base junction is reverse biased only
    2. Bemitter is open circuit
    3. Cgate voltage is below threshold
    4. Dboth junctions are forward biased and VCE is small
    💡 Explanation:

    Saturation: VBE and VBC forward; device acts like closed switch.

  32. Q32easy

    In a common-emitter BJT amplifier, base current controls

    1. Adrain current without gate voltage
    2. Bonly emitter reverse leakage
    3. Clarge collector current via current gain β
    4. Dop-amp offset voltage directly
    💡 Explanation:

    Small IB change modulates IC ≈ βIB in active region.

  33. Q33Past Paper · PPSC/FPSC/NTSmedium

    Rectifier diode selection must consider

    1. Aonly LED color wavelength
    2. Bforward current rating, PIV and switching speed for the application
    3. Conly op-amp slew rate
    4. Donly flip-flop clock frequency without power
    💡 Explanation:

    Thermal, voltage and speed ratings ensure reliable rectification.

  34. Q34medium

    Varactor diode capacitance varies with

    1. Areverse bias voltage
    2. Bforward current only without voltage dependence
    3. Ctemperature only without bias
    4. Dgate threshold in MOSFET sense
    💡 Explanation:

    Depletion width changes with reverse bias modulating capacitance.

  35. Q35Past Paper · PPSC/FPSC/NTShard

    Tunnel (Zener) breakdown dominates in heavily doped junctions at

    1. Avery high reverse voltage only above 100 V always
    2. Bforward conduction region only
    3. Clower reverse voltages (typically below about 5 V in silicon)
    4. Donly in germanium without silicon
    💡 Explanation:

    Thin depletion layer enables quantum tunneling at low Vz.

  36. Q36hard

    Avalanche breakdown in a diode occurs when

    1. Aforward bias exceeds knee slightly only
    2. Bgate oxide ruptures in MOSFET
    3. Conly tunneling without multiplication
    4. Dminority carriers accelerate and create impact ionization
    💡 Explanation:

    Carrier multiplication in high reverse field causes avalanche.

  37. Q37medium

    Diode dynamic resistance rd is defined as

    1. Aslope of V-I curve at the operating point (dv/di)
    2. Breverse saturation current only
    3. Cmaximum forward current rating
    4. Dthermal voltage times beta
    💡 Explanation:

    Small-signal resistance is inverse slope of static characteristic.

  38. Q38Past Paper · PPSC/FPSC/NTSmedium

    Schottky diode has lower forward voltage drop than PN junction diode because

    1. Ait uses only indirect bandgap silicon always
    2. Bit has no depletion region ever
    3. Cmetal-semiconductor junction has smaller barrier height
    4. Dit operates only in Zener breakdown
    💡 Explanation:

    Schottky barrier diodes switch faster with ~0.2–0.4 V drop.

  39. Q39easy

    LED emits light when

    1. Areverse breakdown occurs without recombination
    2. Belectrons and holes recombine at the PN junction
    3. Conly thermal heating without injection
    4. Dgate voltage controls channel only like MOSFET
    💡 Explanation:

    Radiative recombination in direct-bandgap material produces photons.

  40. Q40medium

    Ripple factor of a rectifier output indicates

    1. Aonly DC average without AC content
    2. Breverse breakdown voltage margin
    3. Ctransistor beta value
    4. Damount of AC component relative to DC component
    💡 Explanation:

    Lower ripple factor means smoother DC output.

  41. Q41Past Paper · PPSC/FPSC/NTSeasy

    Full-wave bridge rectifier requires

    1. Atwo diodes and center tap always
    2. Bfour diodes and no center-tapped transformer
    3. Cone diode only
    4. Dsix diodes in star connection
    💡 Explanation:

    Bridge uses four diodes to rectify both half-cycles.

  42. Q42easy

    Half-wave rectifier output contains

    1. Apure DC without any ripple
    2. Bonly one polarity of the input AC waveform
    3. Cboth polarities equally
    4. Donly high-frequency harmonics without fundamental
    💡 Explanation:

    One diode passes alternate half-cycles only.

  43. Q43medium

    Peak inverse voltage (PIV) rating of a rectifier diode is

    1. Amaximum forward current only
    2. Bpower dissipation at room temperature only
    3. Cjunction capacitance at zero bias
    4. Dmaximum reverse voltage the diode can withstand without breakdown
    💡 Explanation:

    PIV defines safe reverse blocking capability.

  44. Q44Past Paper · PPSC/FPSC/NTSeasy

    Zener diode is primarily used for

    1. Arectification in forward region only
    2. Boscillation without feedback
    3. Ccurrent amplification like a BJT
    4. Dvoltage regulation in reverse breakdown region
    💡 Explanation:

    Zener maintains nearly constant voltage in breakdown.

  45. Q45easy

    Reverse saturation current in an ideal silicon diode at room temperature is

    1. Aequal to forward current always
    2. Bvery small (nanoampere range)
    3. Cin the ampere range typically
    4. Dproportional to forward voltage squared only
    💡 Explanation:

    Minority carrier diffusion causes tiny reverse current.

  46. Q46Past Paper · PPSC/FPSC/NTSeasy

    A semiconductor diode conducts heavily when

    1. Areverse biased above breakdown always without limit
    2. Bunbiased at thermal equilibrium only for heavy conduction
    3. Cforward biased beyond knee voltage
    4. Dconnected in parallel with reverse diode only
    💡 Explanation:

    Forward bias reduces barrier; current rises sharply after knee.

  47. Q47hard

    Audio power amplifier heat sink sizing depends on

    1. Aonly voltage gain in dB
    2. Bonly input bias current in pA
    3. Conly LED forward voltage
    4. Dpower dissipation and thermal resistance to ambient
    💡 Explanation:

    Junction temperature must stay below safe limit under load.

  48. Q48medium

    Emitter degeneration resistor without bypass

    1. Amaximizes AC gain unconditionally
    2. Bprevents any collector current flow
    3. Cstabilizes bias and reduces gain but improves linearity
    4. Dreplaces the need for coupling capacitor
    💡 Explanation:

    Negative feedback via RE reduces gain variation with temperature.

  49. Q49Past Paper · PPSC/FPSC/NTSmedium

    Op-amp input offset voltage causes

    1. Asmall DC output error even with zero input signal
    2. Binfinite bandwidth always
    3. Coscillation without any feedback
    4. Dinput impedance to become zero
    💡 Explanation:

    Mismatch in input transistors produces input-referred offset.

  50. Q50easy

    Non-inverting amplifier closed-loop gain is

    1. A1 + Rf/R1
    2. B−Rf/R1 only
    3. CRf/R1 without unity term
    4. Dzero always with feedback
    💡 Explanation:

    Positive input amplified by resistive feedback network.

  51. Q51easy

    Inverting amplifier closed-loop gain is

    1. A1 + Rf/Rin without sign inversion
    2. BRf × Rin product only
    3. Cindependent of feedback resistors
    4. D−Rf/Rin
    💡 Explanation:

    Feedback sets gain to ratio of feedback to input resistors.

  52. Q52Past Paper · PPSC/FPSC/NTSeasy

    Virtual short between inputs of op-amp in negative feedback means

    1. Aboth inputs are physically shorted externally
    2. Binputs carry equal large current always
    3. Cvoltage difference between inputs is approximately zero
    4. Doutput is always saturated
    💡 Explanation:

    High gain forces differential input voltage ≈ 0 in linear region.

  53. Q53easy

    Ideal operational amplifier has

    1. Azero gain and zero input impedance
    2. Binfinite open-loop gain, infinite input impedance and zero output impedance
    3. Cfinite gain of unity only always
    4. Doutput impedance equal to 50 Ω always
    💡 Explanation:

    Ideal op-amp assumptions simplify analysis.

  54. Q54hard

    Safe operating area (SOA) of a transistor specifies

    1. Aonly maximum power at DC only without pulse duty
    2. Bpermissible combinations of voltage and current without damage
    3. Conly beta at one current point
    4. Donly op-amp bandwidth
    💡 Explanation:

    SOA curves include thermal and second-breakdown limits.

  55. Q55Past Paper · PPSC/FPSC/NTSmedium

    FET is preferred in high-input-impedance amplifier front ends because

    1. Agate draws negligible DC current
    2. Bcollector draws maximum base current
    3. Cemitter is always forward biased heavily
    4. Ddrain current equals gate current always
    💡 Explanation:

    Ultra-low gate leakage suits sensor interfaces.

  56. Q56medium

    Darlington pair provides

    1. Aunity voltage gain only without current gain
    2. Bnegative input impedance always
    3. Coscillation without feedback guaranteed
    4. Dvery high current gain with two cascaded transistors
    💡 Explanation:

    Overall β ≈ β1 × β2 for composite device.

  57. Q57hard

    Channel length modulation in MOSFET is analogous to

    1. AEarly effect in BJT
    2. BZener breakdown in diodes only
    3. Chysteresis in Schmitt trigger only
    4. Dsampling aliasing only
    💡 Explanation:

    Short-channel effect raises ID with VDS similar to Early effect.

  58. Q58medium

    Slew rate of an op-amp limits

    1. Amaximum rate of change of output voltage
    2. BDC gain only
    3. Cinput bias current only
    4. Dcommon-mode rejection at DC only
    💡 Explanation:

    Internal current limits cap dVout/dt especially for large steps.